Parallel Computing Hits the Power Wall by Arthur Francisco Lorenzon & Antonio Carlos Schneider Beck Filho

Author:Arthur Francisco Lorenzon & Antonio Carlos Schneider Beck Filho
Language: eng
Format: epub
ISBN: 9783030287191
Publisher: Springer International Publishing

4.3 Dynamic Voltage and Frequency Scaling

4.3.1 Approaches with no Runtime Adaptation and no Transparency

Snowdon et al. [109] and [108] propose a model to predict performance and energy under different DVFS levels. Given a workload execution at one frequency setpoint, the model predicts the runtime and energy at any other CPU frequency setpoint. The model consists of three steps: (1) data sets are generated to calibrate the model using least-squares linear regression; (2) the model is validated through comparison with the measured power and performance; (3) the model is built to predict performance and energy. Results were validated through the execution of different applications from the MiBench suite, SPEC CINT95, and elsewhere on a PXA255 processor, based on an ARMv5T-compatible XScale core. The maximum error for performance prediction was 3.7%, and the average error was 0.72%. As for energy prediction, the maximum error was 4.9%, and the average error was 1.5%.

Rountree et al. [100] present an analytic framework to predict the applications performance under different DVFS configurations. The framework is processor-independent and uses a single performance counter, namely Leading Loads. The approach was validated through the execution of different kernels from the NAS Parallel Benchmarks and SPEC CPU benchmarks, and the results show improvements concerning the accuracy compared to the existing approaches. Mifakhutdinov et al. [81] propose a DVFS performance predictor for realistic memory systems. The framework, CRIT+ BW, considers two variables when predicting the memory performance: memory access latency and effects of prefetching. CRIT+ BW was evaluated using two different application classes from SPEC 2006 benchmarks: memory-intensive and prefetch-heavy. Results show that when CRIT+ BW is used together with DVFS, energy consumption can be saved by up to 65% when compared to the execution without DVFS and CRIT+ BW, while previously DVFS approaches were able to reduce the energy consumption by less than 34%.

Rossi et al. [99] propose an offline approach based on a multiple linear regression model that estimates the power consumption for different DVFS policies: performance, ondemand, and powersave. Then, the programmer can use the predicted values to select the DVFS policy that provides the lowest power consumption. Marques et al. [33] perform an extensive study addressing multidimensional frequency scaling for multicore embedded systems. Different hardware components were evaluated and had the operating frequency changed, such as processor, L2 cache, and RAM. The main idea is to find the combination of frequency for each hardware component that delivers the lowest energy consumption and EDP when running parallel applications. Results showed that by selecting the ideal configuration before the application execution, it is possible to improve the EDP by up to 46.4% when compared to the standard way that frequencies are configured.

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